Many types of memory devices such as Dynamic Random Access Memory (DRAM) devices store information in memory cells arranged as one or more arrays of selectable rows and columns. Lines connecting each row are commonly referred to as word lines. Each column typically comprises two bit lines, each bit line connected to every other memory cell in the column. To accommodate high density memory demands, two levels of sense amplifier circuitry are typically used to read data out of a memory array and off chip. Primary Sense Amplifier (PSA) circuitry directly reads data from an activated row in the array and drives the data onto a local data bus. Secondary Sense Amplifier (SSA) circuitry coupled to the local data bus evaluates the data by sensing voltage levels of the local data bus and driving the sensed data onto a global data bus. The desired data is then driven off chip.
Conventional SSA circuitry typically comprises pairs of cross-coupled differential amplifiers coupled to current source transistors. Each pair of cross-coupled amplifiers senses the voltage difference between its pair of complementary data bus lines when activated during a read operation. The cross-coupled differential amplifiers cannot reliably sense the voltage difference unless provided sufficient current. To this end, each amplifier is coupled to a current source transistor that enables current flow within the SSA circuitry. Sufficient current flows in the differential amplifier circuitry only when all current source transistors are properly biased. If even a single current source transistor is improperly biased, the SSA circuitry functions unreliably.
A single bias circuit is typically provided for biasing all current source transistors included in the SSA circuitry. Consider, for example, a memory device having two 128-bit wide memory arrays. Each memory array has SSA circuitry coupled thereto. Each set of SSA circuitry has 128 pairs of cross-coupled differential amplifiers and 256 current source transistors for providing current to respective ones of the differential amplifiers. The same circuit biases all 512 current source transistors. However, process variation ensures that all current source transistors will not have the same operating characteristics such as threshold voltage. Instead, a distribution of threshold voltages governs operation of the current source transistors.
The SSA circuitry will not function properly unless the current source transistors with a high threshold voltage are biased properly. Conventionally, the operating margin of the bias circuit is set based on a distribution of expected threshold voltages for the current source transistors. The suitability of the memory device for low power applications and applications having stringent temperature requirements suffers when the bias circuit must draw current high enough to ensure proper biasing of the SSA circuitry. Moreover, the SSA circuitry still functions improperly when the actual distribution of actual threshold voltages falls outside the modeled range because operation of conventional SSA bias circuits cannot be adjusted to account for unexpected results.